1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of fabricating the same, or more particularly to a high-integration DRAM using an SOI (Silicon-On-Insulator) substrate and a method of fabricating the same.
2. Description of the Related Art
Examples of conventional high-integration DRAMs are BEST (BuriEd STrap) cells disclosed in L. Nesbit et al., "A 0.6 .mu.m.sup.2 256Mb Trench DRAM Cell With Self-Aligned BuriEd STrap", 1993 IEDM Technical Digest, pp. 627-630, 1993 and G. Bronner et al., "A Fully Planarized 0.25 .mu.m CMOS. Technology for 256 Mbit DRAM and Beyond", 1995 Symposium on VLSI Technology Digest of Technical Papers, pp. 15-16, 1995.
A BEST cell will be described with reference to FIG. 9. A MOSFET having a gate oxide film 42, a gate electrode 43 formed of a superposed film of WSi film/polysilicon film, and source/drain diffusion layers 45 is formed on a P-Well 32 which in turn is formed on a semiconductor substrate. A trench 33 is formed in the vicinity of the MOSFET. A capacitor formed of a buried N-Well 31, an ON film 34 and a polysilicon film 35 is formed in the lower portion of the trench. The ON film includes a SiN film formed on the inner wall of the trench and an oxide film formed of an oxidated surface of the SiN film. An oxide film collar 36 is formed along the inner wall at the middle portion of the trench, and a polysilicon film 37 is formed in the middle portion of the trench. One of the source/drain diffusion layers 45 of the MOSFET is connected to a buried strap (Impurities Diffusion Layer) 40, and further to a polysilicon film 39 through a sidewall contact 38 formed in the upper portion of the trench. The polysilicon films 39, 37, 35 are interconnected and are filled in the trench. A STI (Shallow Trench Isolation) 41 constituting a device-isolating region is formed in the substrate, at one side of the upper portion of the trench, which side is opposite to the other side where the buried strap 40 is formed. A SiN film 44 is formed above the gate electrode 43, and a sidewall spacer 46 is formed on the sidewall of the gate electrode 43 and the SiN film 44. A flattened interlayer BPSG film 47 is formed on the sidewall spacer 46. Also, a SAC (Self-Aligned Contact) 48 is opened to the gate electrode 43 on the other layer of the source/drain diffusion layers 45 of the MOSFET. This SAC 48 is filled with a polysilicon plug 49. A bit wire 50 connected with the polysilicon plug 49 is formed on the interlayer BPSG film 47.
In fabricating the BEST cell, the buried N-Well 31 is formed on an N-semiconductor substrate, and then the trench 33 is formed. The ON film 34 is formed on the inner wall of the trench, by depositing a nitride film on the inner wall of the trench and then oxidating the surface of the nitride film. The polysilicon film 35 is filled in the lower-portion of the trench. The polysilicon film 35 is etched back to the middle portion of the trench, and then the oxide film collar 36 is formed along the inner wall of the trench. The middle portion of the trench is filled again with the polysilicon film 37, and the polysilicon film 37 thus filled is etched back to a predetermined depth, thereby exposing a portion of the oxide film collar 36. The oxide film collar 36 thus exposed is etched off, thereby forming a sidewall contact 38. As the next step, a polysilicon film 39 is buried in the upper portion of the trench, followed by etching back the polysilicon film 39 to the substrate surface. After that, the N-impurities contained in the polysilicon film 39 are diffused into a P-well 32 by heat treatment thereby to form a buried strap 40. Then, a mask layer (not shown) is formed at a predetermined position, and using this mask layer, a predetermined portion of the semiconductor substrate is removed. An STI 41 is formed in this portion left after removal. The P-Well 32 is formed by an ion implantation process. Then, an oxide film layer, a conductive layer and an SiN layer are sequentially formed, and by patterning these layers, the gate oxide film 42, the gate electrode 43 and the SiN film 44 are formed, respectively. With these deposited films as a mask, impurities are implanted in the P-well 32 thereby to form N-type source/drain diffusion layers 45 in the P-well 32. As the next step, the sidewall spacer 46 is formed on the sidewall of the gate electrode, followed by forming the interlayer BPSG film 47 on the sidewall spacer 46 and flattening the BPSG film 47. The SAC 48 is opened to the gate electrode 43 at a portion of the BPSG film 47 corresponding to one of the source/drain diffusion layers, and then the SAC 48 is filled with the polysilicon plug 49. Then, the bit wire 50 connected with the polysilicon plug 49 is formed on the interlayer BPSG film 47.
The above-mentioned conventional BEST cell poses the following problems.
First, in order to secure a sufficiently large capacitance, a deep trench or a thin ON film is required. The effort to increase the aspect ratio of the trench and reduce the thickness of the ON film, however, has almost reached a technical limit, and a further integration is considerably difficult.
Secondly, the use of a MOSFET formed on a bulk silicon layer increases the junction capacity between the source/drain diffusion layers and the substrate, making it impossible to increase the operation speed.
Thirdly, the configuration of a MOSFET formed on a bulk silicon layer cannot reduce power consumption.
Fourthly, the depth of the STI 41 is required to be larger than the sidewall contact 38, which demands a higher controllability and prevents a high-yield production of cells.
Fifthly, the formation of the oxide film collar and the sidewall contact requires complicated processes, and the trench must be buried with a polysilicon film three times, resulting in an increased fabrication cost.